This invention relates to master slice type integrated circuit device and manufacturing method thereof for mutually wiring plural logic function cells depending on the required circuit configuration by preparing multiple logic function cells integrated on a semiconductor substrate as a so-called master slice.
As the number of integrated transistors in a semiconductor device increases, the semiconductor processing technology becomes complicated, and a longer period is needed for production. In the layout design, on the other hand, the computer aided design (CAD) apparatus has been employed in order to cope with the complicated layout processing, and wiring is being automated. A conventional semiconductor device is shown in FIG. 4, in which plural logic function cells 2, 3 are formed on a semicondutor substrate 1, and these logic function cells 2, 3 are connected by a wiring group 4. When connecting such two or more logic functions 2, 3 by wiring, it is sometimes necessary to connect a terminal 2a of one logic function cell 2 and a terminal 3a of the other logic function cell 3, or to connect a terminal 2b of one logic function cell 2 and a terminal 3b of the other logic function cell 3. At this time, crossing parts occur in the wirings to connect between terminals 2a and 3a, and 2b and 3b.
In the prior art, accordingly, a two-layer wiring is used as wiring group 4. That is, a first layer wirings 5, 6 are formed at the positions indicated by broken line in FIG. 4, and an insulation layer 7 is formed on them, and a contact hole 7a is formed in this insulation layer 7, and second layer wirings 8, 9, 19, 11 are formed at the positions indicated by solid line on the insulation layer 7, and part of them is connected to the first layer wirings 5, 6 by way of the contact hole 7a. Thus, the two logic function cells 2, 3 are connected by two layers of wiring, and the crossing part A does not cause any inconvenience because the first layer wiring 6 and second layer wiring 10 are insulated by the insulation layer 7.
In this conventional wiring method, however, at least three steps are needed until completion of wiring, that is, processing of first layer wiring, forming of contact hole in insulation layer, and processing of second layer wiring. Therefore, if the CAD should be employed, the wiring process cannot be shortened, and the term of development after completion of logic design cannot be shortened.